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| Be tR s n (o ds N-CHANNEL 500V - 0.22 - 20A TO-220/I2PAK *Q ) g STP20NM50FD STB20NM50FD-1 FDmeshTM Power MOSFET (with FAST DIODE) VDSS 500V 500V RDS(on) <0.25 <0.25 Rds(on)*Qg 8.36 *nC 8.36 *nC ID 20 A 20 A TYPE STP20NM50FD STB20NM50FD-1 s s s s s s TYPICAL RDS(on) = 0.22 HIGH dv/dt AND AVALANCHE CAPABILITIES 100% AVALANCHE TESTED LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTURING YIELDS 12 3 TO-220 I2PAK (Tabless TO-220) DESCRIPTION The FDmeshTM associates all advantages of reduced on-resistance and fast switching with an intrinsic fastrecovery body diode. It is therefore strongly recommended for bridge topologies, in particular ZVS phaseshift converters. APPLICATIONS ZVS PHASE-SHIFT FULL BRIDGE CONVERTERS FOR SMPS AND WELDING EQUIPMENT INTERNAL SCHEMATIC DIAGRAM s ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (q) PTOT dv/dt(1) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuos) at TC = 25C Drain Current (continuos) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature Value 500 500 30 20 14 80 192 1.2 20 -65 to 150 150 (1)ISD 20A, di/dt 200A/s, VDD V(BR)DSS, Tj TJMAX. (*)Limited only by maximum temperature allowed Unit V V V A A A W W/C V/ns C C (*)Pulse width limited by safe operating area August 2002 1/9 STP20NM50FD/STB20NM50FD-1 THERMAL DATA Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max 0.65 62.5 300 C/W C/W C Maximum Lead Temperature For Soldering Purpose AVALANCHE CHARACTERISTICS Symbol IAR EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 35 V) Max Value 10 700 Unit A mJ ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 30V Min. 500 1 10 100 Typ. Max. Unit V A A nA ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10V, ID = 10A Min. 3 Typ. 4 0.22 Max. 5 0.25 Unit V DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (2) Rg Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Gate Input Resistance VGS = 0V, VDS = 0V to 400V f=1 MHz Gate DC Bias=0 Test Signal Level=20mV Open Drain Test Conditions VDS > ID(on) x RDS(on)max, ID = 10A VDS = 25V, f = 1 MHz, VGS = 0 Min. Typ. 9 1380 290 40 130 2.8 Max. Unit S pF pF pF pF 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 2/9 STP20NM50FD/STB20NM50FD-1 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 250V, ID = 10 A RG = 4.7 VGS = 10V (see test circuit, Figure 3) VDD = 400V, ID = 20A, VGS = 10V Min. Typ. 22 20 38 18 10 53 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Conditions VDD = 400V, ID = 20 A, RG = 4.7, VGS = 10V (see test circuit, Figure 5) Min. Typ. 6 15 30 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (1) trr Qrr IRRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, VGS = 0 ISD = 20 A, di/dt = 100A/s, VDD = 60V, Tj = 150C (see test circuit, Figure 5) 245 2 16 Test Conditions Min. Typ. Max. 20 80 1.5 Unit A A V ns C A Note: 1. Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area For TO-220 / IPAK Thermal Impedance For TO-220 / IPAK 3/9 STP20NM50FD/STB20NM50FD-1 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/9 STP20NM50FD/STB20NM50FD-1 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP20NM50FD/STB20NM50FD-1 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP20NM50FD/STB20NM50FD-1 TO-220 MECHANICAL DATA DIM. MIN. A C D D1 E F F1 F2 G G1 H2 L2 L4 L5 L6 L7 L9 DIA. 13.0 2.65 15.25 6.2 3.5 3.75 0.49 0.61 1.14 1.14 4.95 2.4 10.0 16.4 14.0 2.95 15.75 6.6 3.93 3.85 0.511 0.104 0.600 0.244 0.137 0.147 4.40 1.23 2.40 1.27 0.70 0.88 1.70 1.70 5.15 2.7 10.40 0.019 0.024 0.044 0.044 0.194 0.094 0.393 0.645 0.551 0.116 0.620 0.260 0.154 0.151 mm TYP. MAX. 4.60 1.32 2.72 MIN. 0.173 0.048 0.094 0.050 0.027 0.034 0.067 0.067 0.203 0.106 0.409 inch TYP. MAX. 0.181 0.051 0.107 A C D1 L2 F1 D G1 E Dia. L5 L7 L6 L4 P011C L9 F2 F G H2 7/9 STP20NM50FD/STB20NM50FD-1 TO-262 (I2PAK) MECHANICAL DATA mm MIN. A A1 B B2 C C2 D e E L L1 L2 4.4 2.49 0.7 1.14 0.45 1.23 8.95 2.4 10 13.1 3.48 1.27 TYP. MAX. 4.6 2.69 0.93 1.7 0.6 1.36 9.35 2.7 10.4 13.6 3.78 1.4 MIN. 0.173 0.098 0.027 0.044 0.017 0.048 0.352 0.094 0.393 0.515 0.137 0.050 inch TYP. MAX. 0.181 0.106 0.036 0.067 0.023 0.053 0.368 0.106 0.409 0.531 0.149 0.055 DIM. A C2 B2 B E L1 L2 D L P011P5/E 8/9 e A1 C STP20NM50FD/STB20NM50FD-1 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 9/9 |
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